Peking University’s Analog Solver Reaches FP32 Precision—But It Is No GPU Killer

As of August 2026, Peking University’s analog-computing result remains a specialized matrix-solving demonstration, not a commercially available accelerator capable of replacing Nvidia or AMD GPUs. Follow-up work continues to treat precision, scalability and system integration as research problems, even though the original experiment cleared an important numerical-accuracy barrier.

The central result remains valid, but the headline performance claim needs its experimental boundary. The peer-reviewed research paper, published on October 13, 2025, documents 16 × 16 matrix inversion at 24-bit fixed-point precision, a massive-MIMO test matching an FP32 digital baseline after three iterations, and modelling that reaches up to 1,000 times higher throughput and 100 times better energy efficiency than selected digital processors at equal precision. Those largest advantages are projections for the matrix-solving method, not end-to-end measurements of AI training, inference or graphics.

What the researchers built

The hardware is best understood as an analog matrix-equation solver. It combines a low-precision matrix-inversion circuit, which supplies an approximate answer, with high-precision analog matrix–vector multiplication that calculates the residual error. Repeating those operations progressively refines the solution.

Both computing stages use resistive random-access memory, or RRAM. Electrical conductance programmed into the memory cells represents numerical values, allowing the arrays to store operands and participate directly in computation. This arrangement can reduce the movement of data between separate processing and memory components, although the complete experimental system still requires conversion and control circuitry.

Peking University’s technical account details 3-bit RRAM arrays fabricated on a commercial 40-nanometre CMOS platform, with iterative refinement reaching 24-bit fixed-point precision for the demonstrated matrix problem. The setup also included operational amplifiers, digital-to-analog and analog-to-digital converters, switches, multiplexers and a microcontroller. The result therefore belongs to a coordinated mixed hardware system rather than a single self-contained chip performing every operation.

Why the precision result matters

Analog circuits are attractive because many elements can operate in parallel, but their physical outputs are affected by device variation, electrical noise and limited readout resolution. Matrix inversion is especially sensitive: small errors in stored values or intermediate calculations can produce much larger errors in the final solution. That weakness has restricted analog matrix solvers to small or low-precision tasks.

The Peking University design avoids demanding a perfectly accurate answer from one physical operation. Its inversion stage produces an estimate, while the matrix–vector stage measures how far that estimate is from the required result. Iterative correction then reduces the error, and a block-matrix algorithm divides larger problems into operations that smaller arrays can handle.

This combination is the substantive advance. It shows that low-bit resistive memory can participate in a solver whose final precision approaches a conventional digital format. It does not make the underlying cells intrinsically equivalent to FP32 arithmetic; the accuracy emerges from the arrays, bit slicing, block algorithm, repeated correction and supporting electronics working together.

What the 1,000× comparison actually measures

The comparison concerns equivalent throughput for solving matrix equations under matched precision assumptions. The digital references included Nvidia H100 and AMD Vega 20 GPUs, but GPU throughput was normalized to a single core. That is useful for comparing the scaling of the underlying compute method, yet it is not the same as benchmarking the complete analog setup against an entire GPU with thousands of parallel execution units.

The experimentally demonstrated low-precision inversion array was also smaller than the configurations used for the most ambitious performance estimates. At larger problem sizes, the analysis incorporated block decomposition and modelled circuit behaviour. The highest projected result further assumed faster inversion and multiplication circuitry than the measured setup.

Consequently, “1,000 times faster than Nvidia” removes several decisive qualifiers. A defensible formulation is that the proposed analog solver could reach that order of throughput advantage for a specified matrix-equation workload, at comparable numerical precision, under the paper’s best-case architecture assumptions. It does not establish superior performance for transformer training, language-model inference, rendering, scientific applications as a whole or general-purpose computing.

The energy comparison has the same limit. Conversion circuitry was included in the published model, which makes the analysis more meaningful than an array-only estimate. A deployable accelerator would still need communication links, scheduling, packaging, host integration and software, and its sustained efficiency would have to be measured on representative workloads.

Where this architecture could be useful

The strongest demonstrated use case is massive-MIMO signal detection, where receivers must repeatedly solve structured linear systems to separate signals from multiple antennas. Similar mathematical kernels appear in scientific computing, optimization and some machine-learning methods. A dedicated accelerator could handle compatible matrix operations while digital processors retain control flow, data preparation and unsupported calculations.

That division of labour is more plausible than a wholesale GPU replacement. Modern GPUs are valuable not only for arithmetic throughput but also for programmable execution, mature compilers, high-bandwidth memory, networking and extensively supported software libraries. The experimental solver addresses one demanding mathematical primitive; it does not reproduce that broader platform.

Deployment also requires software capable of deciding which operations belong on analog arrays and compensating for hardware-specific behaviour. Noise sensitivity, weight placement, calibration, fixed or slowly reprogrammable conductance states and communication between analog and digital units all affect real performance.

The status after the original experiment

The later research record reinforces the distinction between a breakthrough component and a finished product. A June 2026 review co-authored by Zhong Sun still presents resistive-memory matrix solvers as part of an evolving field and identifies precision and scalability among its continuing challenges.

The Peking University work therefore matters for a more specific reason than the “impossible chip” label suggests. It demonstrated a credible route to high-precision analog matrix solving on fabricated RRAM hardware and showed why the method could outperform digital computation on selected kernels. Evidence that it can eclipse Nvidia or AMD would require an integrated accelerator, end-to-end application benchmarks and measured advantages that survive outside the laboratory configuration.

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